Method and structure for temporarily isolating a die from a common conductor to facilitate wafer level testing

ABSTRACT

The invention provides a method and apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.

FIELD OF THE INVENTION

[0001] This invention relates generally to the fabrication and testingof semiconductor wafers having discrete semiconductor dice. Morespecifically, the present invention relates to methods of temporarilyisolating semiconductor dice from a common conductor during wafer leveltesting.

BACKGROUND OF THE INVENTION

[0002] In semiconductor manufacture, a large number of often complexelectrical devices, also known as dice or integrated circuit (IC) chips,are fabricated on a semiconductor wafer. After fabrication, the dice aresubjected to a series of test procedures prior to wafer dicing andpackaging to assess the electrical characteristics of the circuitry ofeach. Dice which are determined to meet specifications are allowed tocontinue in the manufacturing process. Those which do not meetspecifications are removed from the manufacturing process.

[0003] One series of testing is known as a “wafer level test,” whichapplies stress conditions to the dice on the wafer in an effort toaccelerate certain types of failures. Wafer level testing may involveelevated voltage, elevated temperature, elevated humidity or any othercondition which a manufacturer deems appropriate to expose failureswhich can be detected using test equipment.

[0004] To facilitate wafer level testing, a common conductor, e.g., abuss, may be provided which interfaces a plurality of dice under testsuch that a signal is propagated to the plurality of dicesimultaneously. One exemplary common conductor may, for example, connectindividual die power inputs to a common power source, e.g., Vcc, Vss.Other common conductors may be used to supply other signals in common tothe dice under test.

[0005] The use of a common conductor to supply a signal to multiple dicehas its drawbacks. When a die is found to be defective, the defectivedie must be isolated from the common conductor(s) so that non-defectivedice are not affected by electrical conditions occurring at thedefective die.

[0006] One way to facilitate high reliability die isolation from acommon conductor is by use of a permanent isolation device, for examplea fuse. A fuse may be interposed between the common conductor and eachdie ensuring permanent isolation from the common conductor when the fuseis blown. While fuses and similar permanent isolation devices providepermanent isolation of a device from a common conductor, they do notpermit a temporary isolation of a die from a common conductor. Thusindividual die isolation and testing cannot be performed withoutpermanently disconnecting a die from the common conductor.

SUMMARY OF THE INVENTION

[0007] The present invention provides a method and apparatus whichfacilitates temporary isolation of a die from one or more commonconductors during wafer level testing. The one or more common conductorsextend over a wafer and are connected to a plurality of dice on thewafers which are undergoing testing. A temporary isolation device (e.g.,a diode, transistor or other element) is interposed between each die andthe common conductor. The temporary isolation device can be used toisolate a die from the common conductor during wafer level testingwhenever such isolation is needed.

[0008] A permanent isolation device may also be provided in the pathbetween each die under test and the common conductor to providepermanent isolation whenever permanent isolation is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other aspects and features of the invention will bebetter understood from the following detailed description which isprovided with the accompanying drawings.

[0010]FIG. 1 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with an exemplaryembodiment of the invention;

[0011]FIG. 2 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with a modified embodimentof the invention;

[0012]FIG. 3 shows a simplified process sequence for isolating andtesting dice using the FIG. 1 or FIG. 2 embodiment of the invention;

[0013]FIG. 4 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention;

[0014]FIG. 5 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention;

[0015]FIG. 6 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention;

[0016]FIG. 7 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention;

[0017]FIG. 8 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention; and

[0018]FIG. 9 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention.

[0019]FIG. 10 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention.

[0020]FIG. 11 shows a simplified schematic diagram of a portion of asemiconductor wafer constructed in accordance with another modifiedembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] The invention provides the capability to perform wafer leveltesting while temporarily isolating a die for testing from other dicewhich are otherwise in electrical communication with a common conductor.In the invention, at least one temporary isolation device is providedbetween each die and a common conductor to temporarily electricallyisolate the die from the common conductor. The temporary isolationdevice may be a diode, transistor or other element. When a diode is usedit can be reverse biased such that the individual die is isolated fromthe common conductor. The invention also provides a temporary isolationtesting system and procedure which is compatible with conventional testequipment already in use.

[0022] Temporary isolation of each unsingulated die on the wafer fromthe common buss can be performed with the invention, such that it may bedetermined if an individual die meets the required specifications thatallow the die to continue in the manufacturing process. If a die isdeemed to not meet the required specifications during this temporaryisolation, it may be subjected to repair or permanent isolation from thecommon conductor.

[0023] To simplify discussion, a fuse will be described as one exemplaryform of a permanent isolation device which can be employed in theinvention, and a diode will be described as one exemplary form of atemporary isolation device. However, it must be understood that any oneof a variety of devices may be used as a permanent and temporaryisolation devices and thus the invention is not limited to fuses ordiodes to accomplish the permanent and/or temporary isolation functions.Non-limiting examples of other permanent isolation devices includeseveral electrical connections or other electrical circuits or deviceswhich permanently isolate a die from a common conductor. Non-limitingexamples of other temporary isolation devices include transistors, orother electrical circuits or devices which can temporarily isolate a diefrom a common conductor.

[0024] Also, for simplicity, a common conductor will be discussed belowas one or more power supply conductors; however, the common conductorcan be used to supply any signal to plural dice connected to it.

[0025] The invention will now be explained with reference to FIGS. 1-10.FIG. 1 discloses one exemplary embodiment of the invention. A portion ofa wafer is shown as containing a plurality of dice 5 which are to betested before die singulation. A common conductor 1 is provided on thewafer and is used to supply a first signal, for example, a positive Vccvoltage, to the individual dice. Likewise, a common conductor 3 isprovided on the wafer and is used to supply a second signal, forexample, a Vss voltage (ground), to the individual dice.

[0026] The common conductors 1 and 3 may supply any signals necessaryfor die operation or testing and thus, as noted, are not limited tosupplying first and second voltage signals, e.g. Vcc and Vss. The commonconductor may be a single conductor or may be part of a group of commonconductors which provide signals to the dice 5.

[0027] A plurality of probe pads 9 are provided in direct electricalcommunication with the common conductor 1, each in proximity to a die 5on the wafer. A probe pad 11 is provided on each die 5 on the wafer inproximity to a probe pad 9 on the wafer. A permanent isolation device 7(e.g. fuse) may be interposed between the common buss 1 and a probe pad11. A probe pad 17 is provided on each die 5 and is connected to, forexample, the normal Vcc voltage input terminal of the die. A temporaryisolation device 19, e.g., diode, is provided on each die 5 between eachprobe pad 17 and probe pad 11. The diode 19 is installed such that it isoperative in a forward bias manner during wafer level testing allowing asignal to pass from common conductor 1 to probe pad 11 and to probe pad17. When temporary isolation is needed, the diode is reverse biasedthereby isolating the die from the common conductor 1.

[0028] A plurality of probe pads 13 are provided in direct electricalcommunication to another common conductor 3 each in proximity to a die 5on the wafer. A probe pad 15 resides on each die 5 in proximity to theclosest probe pad 13 on the wafer. A permanent isolation device 7 (e.g.fuse) may be interposed between each probe pad 13 and a probe pad 15. Aprobe pad 21 is provided on each die 5 and is connected to, for example,the normal Vss voltage input terminal of the die. A temporary isolationdevice 19 (e.g. diode) is installed on the die 5 between each probe pad21 and probe pad 15. The diode 19 is installed such that it is operativein a forward bias manner during wafer level testing allowing a signal topass between probe pad 21 and probe pad 15. When temporary isolation isneeded, the diode 19 is reverse biased thereby isolating the die 5 fromthe common conductor 3. It should be recognized that while FIG. 1 showsa permanent isolation device 7 (e.g. fuse) and a temporary isolationdevice 19 (e.g. diode) interposed between each common conductor and thedie, it may be desirable to also have some common conductors which areconnected directly to the dice 5 without interposed permanent ortemporary isolation devices. Also, although FIG. 1 shows the permanentisolation devices 7 fabricated on the wafer off the dice 5 and thetemporary isolation devices 19 fabricated on the dice, it is possible tofabricate both off the dice 5 or both on the dice 5, or with thetemporary isolation device 19 off the dice 5 and the permanent isolationdevice 7 on the dice. It is also possible to provide the commonconductor on an external interface, e.g. a test head or a probe card,and provide one or both of the permanent isolation device 7 andtemporary isolation device 19 on the external interface.

[0029] As can be seen in FIG. 1, when the diodes 19 between pads 11 and17 and pads 21 and 15 are reverse biased during probe testing proceduresof an individual die, only a small amount of leakage will be observedpassing to the common wafer conductors 1 and 3 through the permanentisolation device, e.g. fuse 7. Accordingly, each die may be individuallytested with a first and second signal, e.g. Vcc and Vss respectivelyprovided through probe pads 17 and 21, without affecting other diceconnected to the common conductors 1 and 3. If during such individualtesting a die is found to be defective, the permanent isolation device 7associated with the defective die may be used by means well known in theart (e.g. fuse blowing) to permanently isolate the die from the commonconductors 1 and 3 thereby enabling the common conductors to effectivelypower the serviceable dice during wafer level testing procedures.

[0030]FIG. 1 shows the permanent isolation device 7, e.g., fuse,provided on a wafer and off the dice 5 and between pads 9 and 11 andbetween pads 13 and 15. However, as noted, the permanent isolationdevice can be provided at other locations, including on each die 5, oron an external interface, between a common conductor 1 and a die signalpad on the die requiring a signal from the common conductor. Moreover,the temporary isolation devices 19, e.g., diodes, may be directlyconnected to a respective common conductor, e.g. 1, 3 with the permanentisolation devices being connected between the temporary isolationdevices and die.

[0031] For example, FIG. 2 shows one alternative embodiment of theinvention where the temporary isolation device 19, e.g. diode, betweenpads 15 and 21 is omitted. FIG. 2 also shows omission of the permanentisolation devices 7, e.g. fuse, between pads 9 and 11 and 13 and 15.Other modified embodiments are described below with reference to FIGS.4-11.

[0032]FIG. 3 shows a simplified processing sequence used for testingeach die 5 in FIG. 1. First, in processing segment 101, single die levelsignals are applied from an external interface to the pads 17 and 11 and21 and 15 to supply signals to the temporary isolation device(s). Otherprobes of the external interface may be applied to other signal pads ofeach die 5 during testing. This reverse biases the diodes used astemporary isolation devices 19, thereby isolating a die 5 from thecommon conductors 1 and 3. In processing segment 103, testing of anisolated die 5 is performed. If the testing reveals that a die 5 shouldbe permanently isolated, then in processing segment 105, the permanentisolation devices 7 are activated, e.g., fuses blown, to permanentlyisolate defective dice 5 from the common conductors 1, 3. As shown inprocessing sequence 107, when the wafer is subjected to wafer leveltesting conditions, including, for example, wafer level burn-in, signalsare applied to conductors 1, 3 which during operation forward bias thediodes 19, permitting common conductors to supply desired signals to alldies still connected to the common conductors. Tests are then conductedwith all dice 5 receiving common signals from the common conductors.

[0033] The processing sequence of FIG. 3 may be varied from that shownto perform testing or other operations which require temporary isolationof dice 5 from one or more common conductors. For example, die isolationand individual die testing using the FIG. 1 embodiment, may beaccomplished after signals arc commonly applied to all dice through thecommon conductors 1 and 3 (segment 107). The permanent isolation devices7, e.g. fuses, can be opened, e.g. fuses blown, either automatically ormanually when defective dice are identified when signals are applied toconductors 1, 3. The permanent isolation devices may also be opened whensignals are applied directly to the die pads 17 and 21 and defectivedevice dice 5 are found. Permanent isolation devices 7, such as fuses,may be activated by use of any technology which is appropriate forproviding permanent isolation of dice from a common conductor. Whenfuses are used, the fuse itself can be automatically blown whenexcessive current passes through it, or it can be opened by laser,mechanical severance, applying a sufficient high voltage across it, orother technique.

[0034]FIGS. 4 through 11 illustrate other alternative embodiments of theinvention. FIG. 4 illustrates an embodiment where the permanentisolation device 7, e.g. a fuse, and a temporary isolation device 19,e.g., a diode, are provided on a wafer between a common conductor 31 anda die 5. Probe pads 33, 35 and 37 are also shown. In this embodiment,both the permanent 7 and temporary 19 isolation devices are provided offdie, for example, in the street area of a wafer.

[0035]FIG. 5 illustrates an embodiment where the permanent isolationdevice 7, e.g. fuse, and temporary isolation device 19, e.g. diode, areprovided on a die 5, and a pair of spaced probe pads 45 a, 45 b are usedwhich can be bridged by a conductor on an external interface to connectdie 5 to common conductor 31. Pad 45 b is provided on the die while pad45 a is provided off the die 5.

[0036]FIG. 6 illustrates an embodiment of the invention in which thepermanent isolation device 7, e.g. a fuse, is provided off the die, thetemporary isolation device 19, e.g. a diode, is provided on the die andspaced pads 45 a, 45 b which can be bridged by a conductor on anexternal interface and which are used to connect die 5 to the commonconductor 31.

[0037]FIG. 7 illustrates an embodiment of the invention in which boththe permanent isolation device 7, e.g. fuse, and the temporary isolationdevice 19, e.g. diode, are provided off the die 5 and a pair of spacedpads 45 a, 45 b which can be bridged with a conductor on an externalinterface which are used to connect die 5 to the common conductor 31.Here pad 45 a is provided off die 5, while pad 45 b is provided on thedie 5.

[0038]FIG. 8 illustrates an embodiment of the invention similar to FIG.4, but where the locations of the permanent and temporary isolationdevices 7, 19 are reversed.

[0039]FIGS. 9 and 10 illustrate embodiments similar to FIG. 4, but werethe temporary isolation device 19′ is shown as a transistor connected asa diode. FIGS. 9 and 10 differ in the type of transistor and associatedconnections which make it function as a diode.

[0040]FIG. 11 illustrates an embodiment similar to FIG. 4, but where thetemporary isolation device 19″ is a controlled transistor with thecontrol signal being supplied via a probe pad 43. The applied controlsignal may originate at an external interface.

[0041] While the invention has been described and illustrated withrespect to one or more common conductors, e.g. 1, 3, 31, which areprovided on a wafer, the common conductors can instead be provided on anexternal interface used during wafer level testing.

[0042] Also, during temporary isolation, individual dice 5 may be testedin a predefined order or simultaneously.

[0043] While exemplary embodiments of the invention have been describedand illustrated, it should be evident that many alterations,modifications and variations can be made without departing from thespirit or scope of the invention. Accordingly, the invention is not tobe considered as limited by the descriptions and illustrations provided,but is only limited by the scope of the appended claims.

What is claimed is:
 1. A die test apparatus comprising: a plurality ofdice fabricated on a wafer a common signal line for applying a signal incommon to said plurality of dice; and a plurality of temporary isolationdevices respectively provided between said common signal line and saidplurality of dice, each said temporary isolation device permitting anassociated die to be temporarily disconnected from said common signalline.
 2. An apparatus of claim 1 wherein said temporary isolation deviceis a unidirectional current device.
 3. An apparatus of claim 2 whereinsaid temporary isolation device is a diode.
 4. An apparatus of claim 2wherein said temporary isolation device is a transistor.
 5. An apparatusof claim 4 wherein said transistor is connected as a diode.
 6. Anapparatus of claim 4 wherein said transistor is connected to becontrolled by an applied signal.
 7. An apparatus of claim 1 wherein saidcommon signal line supplies a power supply signal to said dice.
 8. Anapparatus of claim 1, further comprising a plurality of permanentisolation devices respectively provided in series with said plurality oftemporary isolation devices, each said permanent isolation device beingcapable of providing permanent isolation between said common signal lineand a respective die.
 9. An apparatus of claim 8, wherein each saidpermanent isolation devices comprises a fuse.
 10. An apparatus of claim1 wherein said common signal line is provided on said wafer.
 11. Anapparatus of claim 1 further comprising an external interface fortesting said plurality of dies and wherein said common signal line isprovided on said external interface.
 12. An apparatus of claim 1 whereineach said temporary isolation device is provided off an associated die.13. An apparatus of claim 12 wherein each said temporary isolationdevice is provided on said wafer.
 14. An apparatus of claim 13 whereineach said temporary isolation device is provided in a street area ofsaid wafer.
 15. An apparatus of claim 12 wherein each said temporaryisolation device is provided at an external interface for testing saidplurality of dies.
 16. An apparatus of claim 1 wherein each temporaryisolation device is provided on a respective die.
 17. An apparatus ofclaim 8 wherein each said permanent isolation device is provided off arespective die.
 18. An apparatus of claim 17 each said permanentisolation device is provided on said wafer.
 19. An apparatus of claim 18each said permanent isolation device is provided in a street area ofsaid wafer.
 20. An apparatus of claim 17 where each said permanentisolation device is provided at an external interface for testing saidplurality of dies.
 21. An apparatus of claim 8, wherein each permanentisolation device is provided on a respective die.
 22. An apparatus ofclaim 1 further comprising a pair of shortable spaced terminals in anelectrical path between each said die and said common conductor.
 23. Anapparatus of claim 22 wherein a first one of said spaced terminals isprovided on a said die and a second one of said terminals is providedoff said die.
 24. An apparatus of claim 23 wherein said second one ofsaid terminals is provided in a street area of said wafer.
 25. Asemiconductor wafer comprising: a first signal line provided along saidwafer for supplying a first signal; a plurality of dice fabricated onsaid wafer, each comprising an integrated circuit and a first terminalused to apply a first signal to internal components of said die; and aplurality of unidirectional circuit devices, each coupled between saidfirst common conducting line and a first terminal of a respective diefor allowing a signal to move in only one direction between said firstline and the first terminal of a respective die.
 26. A wafer of claim 25wherein said unidirectional circuit devices are provided on a respectivedice.
 27. A wafer of claim 25 wherein said unidirectional circuitdevices are provided off a respective dice.
 28. A wafer of claim 25further comprising a plurality of permanent isolation devicesrespectively interposed between said signal line and each said die. 29.A wafer of claim 28 wherein said permanent isolation devices arerespectively provided on said dice.
 30. A wafer of claim 28 wherein saidpermanent isolation devices are provided off said dice.
 31. A wafer ofclaim 25 wherein each unidirectional circuit device is a diode.
 32. Awafer of claim 25 wherein each unidirectional circuit device is atransistor.
 33. A wafer of claim 25 wherein the first signal linecomprises a power supply line.
 34. A semiconductor wafer comprising: aplurality of individual dice containing respective integrated circuits;at least a first signal conductor provided on said wafer for supplyingat least a first voltage to each die; each die comprising: circuitry forperforming an electrical function; and a temporary isolation deviceconnected between said first signal conductor and said circuitry fortemporarily isolating said circuitry from said first conductor.
 35. Awafer of claim 34 wherein said temporary isolation device is a diode.36. A wafer of claim 34 wherein said temporary isolation device is atransistor.
 37. A method of testing a plurality of dice fabricated on awafer, said method comprising: connecting a first terminal of each ofsaid plurality of dice to a common signal conductor through respectivetemporary isolation devices which allow said dice to receive a signalfrom said common signal conductor during a first test procedure; andconnecting said first terminal of at least some of said plurality ofdice to another conductor during a second test procedure, said temporaryisolation devices being activated during said second test procedure toisolate said first terminal of said at least some of said dice from saidcommon signal conductor during said second test procedure.
 38. A methodof testing a semiconductor die on a wafer comprising: (1) applyingvoltage to a first voltage line which connects with a plurality of diceon said wafer through respective temporary isolation devices; (2)removing voltage from said first voltage line; and (3) applying voltageto a die by connecting a probe to a first voltage terminal associatedwith said die, said die being isolated from said first voltage line by arespective temporary isolation device.
 39. A method of claim 38 whereinsteps (1) and (2) are performed before step (3).
 40. a method of claim37 further comprising permanently isolating a die from said common firstvoltage conductor as a result of tests performed in said first or secondtest procedure.
 41. A method of claim 38 wherein step (1) is performedafter steps (2) and (3).